crc8.vhd

多项式为x^8+x^5+x^4+1的CRC（循环冗余校验码）的FPGA设计。

library ieee;
use ieee.std_logic_1164.all;
entity crc8 is
port(
     clk:in std_logic;
     rst:in std_logic;
     datain: in std_logic;
     rstout:out std_logic;     
     dataout: out std_logic
    );
end crc8;
architecture behav of crc8 is
signal temp,datain_temp: std_logic_vector(7 downto 0);
signal flag:std_logic;
signal i:integer range 0 to 24;
signal cnt: integer range 0 to 9;
begin
process(clk,rst)
begin  
if rst='0' then
temp<="00000000"; i<=0;dataout<='0';flag<='0';
elsif clk'event and clk='1' then      
      if i=24 then
     temp<="00000000"; i<=0;dataout<='0';flag<='0';
     elsif i<24 then i<=i+1;      
     temp(1)<=temp(0);
     temp(2)<=temp(1);
     temp(3)<=temp(2);
     if flag='1' then
          temp(4)<=temp(3);
          temp(5)<=temp(4);
          temp(0)<=datain;
     else  
     temp(0)<=(datain xor temp(7));
     temp(4)<=(temp(3)xor temp(7));
     temp(5)<=(temp(4)xor temp(7));
     end if;     
     temp(6)<=temp(5);
     temp(7)<=temp(6);--x^8+x^5+x^4+1;     
     datain_temp(0)<=datain;
     datain_temp(1)<=datain_temp(0);
     datain_temp(2)<=datain_temp(1);
     datain_temp(3)<=datain_temp(2);
     datain_temp(4)<=datain_temp(3);
     datain_temp(5)<=datain_temp(4);
     datain_temp(6)<=datain_temp(5);
     datain_temp(7)<=datain_temp(6);
     if i>15 then  flag<='1';--did'nt include feedback 
     else flag<='0';--include feedback
     end if;  
     if i>16 then dataout<=temp(7);           
     else dataout<=datain_temp(7);
     end if;
     end if;  
    
  end if;
end process;
process(clk,rst)
begin
if rst='0' then cnt<=0;rstout<='0';
elsif clk'event and clk='0' then 
   if cnt<8 then 
   cnt<=cnt +1;rstout<='0';
   else rstout<='1';cnt<=9;
   end if;
end if;
end process; 
end behav;