代码搜索：ctrl
找到约 10,000 项符合「ctrl」的源代码
代码结果 10,000
www.eeworm.com/read/344792/11860091
v fre_ctrl.v
module fre_ctrl(clk,rst,count_en,count_clr,load);
output count_en,count_clr,load;
input clk,rst;
reg count_en,load;
always @(posedge clk)
begin
if(rst)
begin count_en=0; load=1; end
www.eeworm.com/read/258433/11864831
v mem_ctrl.v
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// All Rights Reserved
////////////////////////////////////////////////////////////
www.eeworm.com/read/344549/11873543
vhd pi_ctrl.vhd
library ieee;
use ieee.std_logic_1164.all;
entity pi_ctrl is
port( clk : in std_logic; --- slow clock
datain : in std_logic_vector( 11 downto 0 );
pwmout : out std_logic_vector( 11 downto
www.eeworm.com/read/258099/11883938
c ctrl_set.c
#include "inc\44b0x.h"
#include "DataType.h"
#define EXT_OSC_CLK 10000000
unsigned int MCLK = 20000000;
void ChangePllValue(int mdiv, int pdiv, int sdiv)
{
int i = 1;
rPLLCON = (md
www.eeworm.com/read/258099/11883956
o ctrl_set.o
www.eeworm.com/read/258099/11883974
h ctrl_set.h
#ifndef __CTRL_SET_H
#define __CTRL_SET_H
#include "44b0x.h"
#include "DataType.h"
void ChangePllValue(int, int, int);
void PortInit(void);
void RtcSetDay(TIME_STRUC *time);
void RtcSet
www.eeworm.com/read/155118/11897882
cpp network_ctrl.cpp
///////////////////////////////////////////////////////
// FileName: network_ctrl.cpp
// Author: b1gm0use
// Project: myvideo
#include
#include
#include "network_ctrl
www.eeworm.com/read/155118/11898059
h network_ctrl.h
///////////////////////////////////////////////////////
// FileName: network_ctrl.h
// Author: b1gm0use
// Project: myvideo
#ifndef _NETWORK_CTRL_H_
#define _NETWORK_CTRL_H_
#include
#
www.eeworm.com/read/344164/11905467
c rf_ctrl.c
/*
* Copyright (c) 1995 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Mark Holland
*
* Permission to use, copy, modify and distribute this software and
* its documentation is h
www.eeworm.com/read/257336/11933652
v fre_ctrl.v
module fre_ctrl(clk,rst,count_en,count_clr,load);
output count_en,count_clr,load;
input clk,rst;
reg count_en,load;
always @(posedge clk)
begin
if(rst)
begin count_en=0; load=1; end