mem_ctrl.v

xilinx公司的ＤＤＲ实现源码

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: 1.0
//  \   \         Filename: addr_gen.v
//  /   /         Timestamp: 12 Dec 2005
// /___/   /\     
// \   \  /  \
//  \___\/\___\
//
//
//Device: Virtex-5
///////////////////////////////////////////////////////////////////////////////

`define simulation 

module mem_ctrl(
input          clk0,
input          rst,
input [35:0]   af_addr,
input          af_empty,
input          first_calib_done,
input          second_calib_done,
input          phy_init_initialization_done,
   
   
output         ctrl_ref_flag,
output         ctrl_af_rden,
output  reg       ctrl_wdf_rden,
output         ctrl_dqs_rst,
output         ctrl_dqs_en,

output         ctrl_wren,
output         ctrl_rden,
output[`row_address-1:0]   ctrl_address,
output[`bank_address-1:0]    ctrl_ba,
output         ctrl_ras_n,
output         ctrl_cas_n,
output         ctrl_we_n,
output [`cs_width-1:0]   ctrl_cs_n,
output reg [`odt_width-1:0]   ctrl_odt,
output [2:0] burst_length

                   );
      

wire           ref_flag;
reg            auto_ref_r;
reg [4:0]      next_state;
reg [4:0]      state_r;
reg [4:0]      state_r1;
reg [4:0]      state_r2;
reg [`row_address -1:0]     row_addr_r ;
reg [`row_address -1:0]     ddr2_address_r;   
reg [`bank_address-1:0]     ddr2_ba_r;


// counters for ddr controller
reg [2:0]      rp_count_r;
reg [5:0]      rfc_count_r;
reg [2:0]      rcd_count_r;
reg [3:0]      ras_count_r;
reg [3:0]      wr_to_rd_count_r;
reg [3:0]      rd_to_wr_count_r;
reg [3:0]      rtp_count_r; 
reg [3:0]      wtp_count_r; 

reg [11:0]      refi_count_r;
reg [2:0]      cas_count_r;   
reg [3:0]      cas_check_count_r;
reg [2:0]      wrburst_cnt_r;
reg [2:0]      read_burst_cnt_r;
reg [2:0]      ctrl_wren_cnt_r;
reg [2:0]      rdburst_cnt_r;   
reg [35:0]     af_addr_r ;
reg [35:0]     af_addr_r1 ;
wire            af_rden;
reg            ddr2_ras_r1;
reg            ddr2_cas_r1;
reg            ddr2_we_r1; 
reg            ddr2_ras_r;
reg            ddr2_cas_r;
reg            ddr2_we_r; 
reg[3:0]       idle_cnt_r;
reg 		conflict_resolved_r;
reg [`cs_width-1:0] ddr2_cs_r2;
reg [`cs_width-1:0]      ddr2_cs_r1;  
reg [`cs_width-1:0]      ddr2_cs_r;
reg [1:0]      chip_cnt_r;
reg [2:0]      auto_cnt_r;
wire[2:0]    burst_cnt;
reg          ctrl_write_en;
reg 	     ctrl_read_en;
reg [3:0]    odt_cnt_r;
reg [3:0]    odt_en_cnt_r;
reg [`odt_width-1 :0 ]         odt_en;
wire         conflict_detect;
reg 	     conflict_detect_r;
wire [14:0] load_mode_reg;
wire [14:0] ext_mode_reg;
reg            WR;
reg            RD;
reg            WR_r;
reg            RD_r;
wire [1:0]     command_address;
wire [3:0]     zeroes;    
reg burst_write;
reg burst_read;
reg burst_write_r;
reg burst_read_r;
reg burst_read_r1;
reg burst_read_r2;
reg [`bank_address+`row_address :0]      bank_00_r;
reg [`bank_address+`row_address :0]      bank_01_r;
reg [`bank_address+`row_address :0]      bank_10_r;
reg [`bank_address+`row_address :0]      bank_11_r;
reg [2:0]                       precharge_bank_r;
reg                             no_precharge_r;
reg                             bank_hit;
reg                             bank_hit0;
reg                             bank_hit1;
reg                             bank_hit2;
reg                             bank_hit3;
reg                             bank_hit0_r;
reg                             bank_hit1_r;
reg                             bank_hit2_r;
reg                             bank_hit3_r;
reg                             bank_hit_r;
reg                             bank_conf_r;
wire                            bank_conflict;
wire                            command;
reg                             phy_init_initialization_done_r;
   wire 			reg_val;
   wire 			[2:0]               cas_lat;
   wire [2:0] 					    brst_lnth;
   wire [2:0] 					    add_lat;
   wire                                             ecc_val;

reg            wdf_rden_r;
reg            wdf_rden_r2;
reg            wdf_rden_r3;
reg            wdf_rden_r4;
   reg 	       dqs_en;
   reg         dqs_reset;

   

 
  reg          ctrl_wdf_read_en;
   reg          ctrl_wdf_read_en_r1;
   reg          ctrl_wdf_read_en_r2;
   reg          ctrl_wdf_read_en_r3;
   reg          ctrl_wdf_read_en_r4;
   reg          ctrl_wdf_read_en_r5;
   reg          ctrl_wdf_read_en_r6;
   
   
   reg [2:0] 	ba,ba1;
   

 

localparam  IDLE                =     5'h00;  
localparam  PRECHARGE           =     5'h01;
localparam  PRECHARGE_WAIT      =     5'h02;
localparam  AUTO_REFRESH        =     5'h03;
localparam  AUTO_REFRESH_WAIT   =     5'h04;
localparam  ACTIVE              =     5'h05;
localparam  ACTIVE_WAIT         =     5'h06;
localparam  BURST_READ          =     5'h07;
localparam  READ_WAIT           =     5'h08;
localparam  BURST_WRITE         =     5'h09;
localparam  WRITE_WAIT          =     5'h0A;
localparam  COMMAND_WAIT        =     5'h0B;
localparam  WRITE_BANK_CONF     =     5'h0C;
localparam  READ_BANK_CONF      =     5'h0D;
localparam  COMMAND_WAIT_CONF   =     5'h0E;
localparam  PRECHARGE_WAIT1     =     5'h0F;
   

assign    reg_val = `registered; 
assign    cas_lat = load_mode_reg[6:4];
assign    brst_lnth = load_mode_reg[2:0];
assign    add_lat = ext_mode_reg[5:3];
assign    odt_enable = ext_mode_reg[2] | ext_mode_reg[6];
assign    ecc_val=	`ecc_enable;
   
assign    burst_length = burst_cnt;
assign    command_address =   af_addr[33:32];
assign    zeroes = 4'b0000;
assign    load_mode_reg         = `load_mode_register;
assign    ext_mode_reg         = `ext_load_mode_register;
   
   
 
// fifo control signals

assign ctrl_af_rden = af_rden;               
   assign conflict_detect = |af_addr[35:34] & ~af_empty;
   assign bank_conflict =   |af_addr[35:34] ; //& ~af_empty; 

   


//commands

always @(*)
  begin
     WR = 1'b0;
     RD = 1'b0;
     bank_hit0 = bank_hit0_r;
     bank_hit1 = bank_hit1_r;
     bank_hit2 = bank_hit2_r;
     bank_hit3 = bank_hit3_r;
     if(~af_empty)
       begin
	  ba = af_addr[`bank_range_end:`bank_range_start];
	  ba1 = bank_10_r[`row_address+`bank_address:`row_address];
        case(command_address)
          2'b00: WR  = 1'b1;
          2'b01: RD  = 1'b1;
        endcase // case(af_addr[31:29])

	  bank_hit0 = (bank_00_r[`row_address+`bank_address:`row_address] == {1'b1, af_addr[`bank_range_end:`bank_range_start]}) ;
          bank_hit1 = (bank_01_r[`row_address+`bank_address:`row_address] == {1'b1, af_addr[`bank_range_end:`bank_range_start]}) ;
          bank_hit2 = (bank_10_r[`row_address+`bank_address:`row_address] == {1'b1, af_addr[`bank_range_end:`bank_range_start]}) ;
          bank_hit3 = (bank_11_r[`row_address+`bank_address:`row_address] == {1'b1, af_addr[`bank_range_end:`bank_range_start]});
     end // if (ctrl_init_done & ~af_empty)
  end // always @ (af_addr)

// register address outputs
always @ (posedge clk0) begin
  if (rst) begin    
     WR_r <= 1'b0;
     RD_r <= 1'b0;
  end else begin
     WR_r <= WR;
     RD_r <= RD;
  end
end
   

// register address outputs
always @ (posedge clk0) begin
  if (rst) begin    
     af_addr_r          <= 36'h00000;
     af_addr_r1         <= 36'h00000;
     conflict_detect_r   <= 1'b0;
  end else begin
     af_addr_r <= af_addr;
     af_addr_r1 <= af_addr_r;
     conflict_detect_r <= conflict_detect;
  end
end

 
always@(posedge clk0) begin
   if (rst) begin
      bank_conf_r <= 1'd0;
      bank_hit0_r <= 1'd0;
      bank_hit1_r <= 1'd0;
      bank_hit2_r <= 1'd0;
      bank_hit3_r <= 1'd0;
      bank_hit_r  <= 1'd0;
      no_precharge_r <= 1'd0;
   end
   else
     begin
	bank_hit_r <= bank_hit0 | bank_hit1 | bank_hit2 | bank_hit3;
	bank_hit0_r <= bank_hit0;
	bank_hit1_r <= bank_hit1;
	bank_hit2_r <= bank_hit2;
	bank_hit3_r <= bank_hit3;
    //  if(~af_empty)
     // begin
           no_precharge_r <= 1'd0;
           bank_conf_r <= bank_conflict; // if no bank hit it becomes a conflict

        casex({bank_conflict,bank_hit0,bank_hit1,bank_hit2,bank_hit3}) // detect bank conf
          5'b11000:bank_conf_r <= (bank_00_r[`row_address-1'b1:0] !=  af_addr[`row_range_end:`row_range_start]);// if bank hit and the row is not open then conflict
          5'b10100:bank_conf_r <= (bank_01_r[`row_address-1'b1:0] !=  af_addr[`row_range_end:`row_range_start]);
          5'b10010:bank_conf_r <= (bank_10_r[`row_address-1'b1:0] !=  af_addr[`row_range_end:`row_range_start]);
          5'b10001:bank_conf_r <= (bank_11_r[`row_address-1'b1:0] !=  af_addr[`row_range_end:`row_range_start]);
          5'b10000:no_precharge_r <= ~bank_11_r[`row_address+`bank_address];
          5'b0xxxx:no_precharge_r <= ~conflict_detect;
          endcase
      //  end
       if ((state_r1 == ACTIVE_WAIT))
        bank_conf_r <= 1'd0;
     end // else: !if(rst)
end // always@ (posedge clk0)
   
   
    
always @ (posedge clk0) begin
  if ((rst) || (state_r1 == AUTO_REFRESH)) begin
      bank_00_r <= `bank_address+`row_address'd0;
      bank_01_r <= `bank_address+`row_address'd0;
      bank_10_r <= `bank_address+`row_address'd0;
      bank_11_r <= `bank_address+`row_address'd0;
      precharge_bank_r <= 3'd0;

  end else begin
     if((state_r == BURST_READ) || (state_r == BURST_WRITE))
       begin
           bank_00_r[`bank_address+`row_address-1'b1:0] <= af_addr_r[`bank_range_end:`row_range_start]; // 00 is always going to have the latest bank and row.
           bank_00_r[`bank_address+`row_address] <= 1'b1; // This indicates the bank was activated

           if(bank_hit1_r)
             bank_01_r <= bank_00_r;
           else if (bank_hit2_r)
             begin
                bank_01_r <= bank_00_r;
                bank_10_r <= bank_01_r;
             end
           else if(~bank_hit0_r) // if no bank hit or bank3 hit.
             begin
                bank_01_r <= bank_00_r;
                bank_10_r <= bank_01_r;
                bank_11_r <= bank_10_r;
             end
       end

       if ((state_r1 == PRECHARGE)) // in case of bank miss, store the LRU bank to precharge
          precharge_bank_r <= bank_11_r[`bank_address+`row_address-1'b1:`row_address];
  end // else: !if(rst)
end // always @ (posedge clk266)
  
 
      
// rp count
always @ (posedge clk0) begin
   if (rst)
       rp_count_r <= 3'd0;
   else if ((state_r == PRECHARGE) )
       rp_count_r <= `rp_count_value;
   else if (rp_count_r > 3'd0) 
     rp_count_r <= rp_count_r - 1'b1;
end

// rfc count
always @ ( posedge clk0) begin
   if (rst)
       rfc_count_r <= 6'd0;
   else if ((state_r == AUTO_REFRESH) )
       rfc_count_r <= `rfc_count_value;
   else if (rfc_count_r > 6'd0)
       rfc_count_r <= rfc_count_r - 1'b1;
end
      
// rcd count - 20ns
always @ ( posedge clk0) begin
   if (rst)
       rcd_count_r <= 3'd0;
   else if (state_r == ACTIVE  )
       rcd_count_r <= `rcd_count_value - add_lat;