pi_ctrl.vhd

VHDL实现PI调节的算法。内部使用整数计算

library ieee;
use ieee.std_logic_1164.all;

entity pi_ctrl is
port( 	clk : in std_logic;  --- slow clock
		datain : in std_logic_vector( 11 downto 0 );
		pwmout : out std_logic_vector( 11 downto 0)
		);
end entity ;

architecture bhv of pi_ctrl is
begin
process( clk )

constant geiding : integer :=2457;  --    1.5/2.5*4096=2457.6 ; 1/2.5*4096 = 1638.4

variable datain_temp : bit_vector ( datain'range);  -- datain converse to bit_vecotr
variable datain_int: integer range 0 to 4096;


constant Ki : integer := 1;
constant Kp : integer := 1;
variable Ek : integer range -4096 to 4096;
variable Ek_1 : integer range -4096 to 4096;
variable d_Ek : integer range -4096 to 4096;
variable Uk : integer range -4096 to 4096;
variable Uk_1 : integer range -4096 to 4096;

variable  pwmout_temp : integer range 0 to 4096 ;
variable pwmout_vec : std_logic_vector ( pwmout'range );




begin
if clk'event and clk = '1' then 
	
	datain_temp := to_bitvector(datain);
	for index in datain'range loop
		datain_int := datain_int * 2 + bit'pos(datain_temp(index));
	end loop;       -- converse input type from std_logic_vector to integer;
	
	Ek := geiding - datain_int;		-- -------------------PI  
	d_Ek := Ek - Ek_1 ;
	Uk := Ki * Ek + Kp * d_Ek + Uk_1 ;
	
	
	
	
	Ek_1 := Ek;
	Uk_1 := Uk;
	
------------------------PWM operation ---------------------------------------------
	




--------------------------------------------the question of negative OR postive --------------
--------------------------------how to show negative to PWM-------------------------------------	
	
	pwmout_temp := Uk  ;  
	                     
	for index in pwmout_vec'reverse_range loop  -----converse integer to std_logic_vector output 
		pwmout_vec( index ) := to_x01(bit'val(pwmout_temp rem 2 ));
		pwmout_temp := pwmout_temp / 2 ;
		exit when pwmout_temp = 0 ;
	end loop;
-------------------------------------------------------------------------------------------	
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	pwmout <= pwmout_vec ;


end if ;
end process;
end bhv;