代码搜索：ctrl
找到约 10,000 项符合「ctrl」的源代码
代码结果 10,000
www.eeworm.com/read/488430/6487092
ctl ctrl_skinablebutton.ctl
VERSION 5.00
Begin VB.UserControl ctrl_SkinableButton
BackStyle = 0 '透明
ClientHeight = 360
ClientLeft = 0
ClientTop = 0
ClientWidth = 1290
www.eeworm.com/read/488430/6487095
ctl ctrl_skinableform.ctl
VERSION 5.00
Object = "{831FDD16-0C5C-11D2-A9FC-0000F8754DA1}#2.0#0"; "MSCOMCTL.OCX"
Begin VB.UserControl ctrl_SkinableForm
BackStyle = 0 '透明
ClientHeight = 750
ClientLeft
www.eeworm.com/read/488430/6487097
ctl ctrl_progressbar.ctl
VERSION 5.00
Begin VB.UserControl ctrl_ProgressBar
AutoRedraw = -1 'True
BackStyle = 0 '透明
ClientHeight = 480
ClientLeft = 0
ClientTop = 0
www.eeworm.com/read/486068/6542941
gif prog_ctrl.gif
www.eeworm.com/read/483608/6599646
v fre_ctrl.v
module fre_ctrl(clk,rst,count_en,count_clr,load);
output count_en,count_clr,load;
input clk,rst;
reg count_en,load;
always @(posedge clk)
begin
if(rst)
begin count_en=0; load=1; end
www.eeworm.com/read/483301/6603445
v idelay_ctrl.v
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This text/file contains proprietary, confidential
// information of Xilinx, Inc., is d
www.eeworm.com/read/483301/6603485
v idelay_ctrl.v
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This text/file contains proprietary, confidential
// information of Xilinx, Inc., is d
www.eeworm.com/read/481648/6636920
v fre_ctrl.v
module fre_ctrl(clk,rst,count_en,count_clr,load);
output count_en,count_clr,load;
input clk,rst;
reg count_en,load;
always @(posedge clk)
begin
if(rst)
begin count_en=0; load=1; end
www.eeworm.com/read/481186/6644363
vhd ctrl_pwm.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity ctrl_PWM is
port(
LA: IN STD_LOGIC_VECTOR(4 DOWNTO 0); --local bus address
www.eeworm.com/read/479927/6683751
v fre_ctrl.v
module fre_ctrl(clk,rst,count_en,count_clr,load);
output count_en,count_clr,load;
input clk,rst;
reg count_en,load;
always @(posedge clk)
begin
if(rst)
begin count_en=0; load=1; end