ctrl_pwm.vhd

舵机控制源程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity ctrl_PWM is
port(
	LA:		IN		STD_LOGIC_VECTOR(4 DOWNTO 0);		--local bus address
	LD:		INOUT	STD_LOGIC_VECTOR(11 DOWNTO 0);	--local data bus
	CS1_L:	IN		STD_LOGIC;	--PLX9052 ChipSelect signal
	LWR_L:	IN		STD_LOGIC;	--local bus write enable signal	
	LRD_L:	IN		STD_LOGIC;	--local bus read enable signal
	LCLK:	IN		STD_LOGIC;	--local bus clock
	LRST_L:	IN		STD_LOGIC;	--local bus reset
	LBE0_L:	IN		STD_LOGIC;
	CLK_1M:	IN		STD_LOGIC;	--1MHz clock signal input from crystal oscillation
	LINT:	OUT		STD_LOGIC;	--local bus int
	PWM:	OUT		STD_LOGIC;	--pulse width modulate signal output
	LRDYI_L:OUT		STD_LOGIC
	);
end ctrl_PWM;

architecture rtl of ctrl_PWM is

signal width		:std_logic_vector(11 downto 0):="010111011100";--1500,1.5ms
signal reg_width	:std_logic_vector(11 downto 0):="000000000000";
signal data			:std_logic_vector(11 downto 0):="000000000000";
signal result		:std_logic_vector(11 downto 0):="000000000000";
signal start			:std_logic:='0';
signal cycle			:std_logic_vector(14 downto 0):="000000000000000";--100111000011111:19999
signal width_start_flag	:std_logic:='0';
constant VCC	:std_logic:='1';
constant GND	:std_logic:='0';

component bustri
port(
		data		: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
		enabledt	: IN STD_LOGIC ;
		enabletr	: IN STD_LOGIC ;
		result		: OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
		tridata		: INOUT STD_LOGIC_VECTOR (11 DOWNTO 0)
	);
end component;
	
begin

bus_buff:bustri
port map(
		data	=>data,
		enabledt=>not(LRD_L),
		enabletr=>not(LWR_L),
		result	=>result,
		tridata	=>LD
		);
	
--L1:process(LRST_L,LCLK)
--begin
--	if LRST_L='0' then
--		width<="010111011100";
--		--reg_width<="000000000000";
--		--cycle<="000000000000000";
--	elsif CS1_L='0' and LA="00000" and LWR_L='0' and LBE0_L='0' then--addr:00 write 1,start to output PWM;
--		if rising_edge(LCLK) then			                   --write 0,stop to output PWM;
--			start<=result(0);
--		end if;
--	elsif CS1_L='0' and LA="00010" and LWR_L='0' then--addr:10 write the Pusle Width:500~2500
--		if rising_edge(LCLK) then
--			width<=result;
--		end if;
--	elsif CS1_L='0' and LA="00010" and LRD_L='0' then--addr:10 read the Pusle Width;
--		if rising_edge(LCLK) then
--			data<=width;
--		end if;
--	end if;
--end process;
L1:process(LRST_L,LCLK)
begin
	if LRST_L='0' then
		width<="010111011100";
		--reg_width<="000000000000";
		--cycle<="000000000000000";
	elsif rising_edge(LCLK) then
		if CS1_L='0' and LA="00000" and LWR_L='0' and LBE0_L='0' then--addr:00 write 1,start to output PWM;
		--if rising_edge(LCLK) then			                   --write 0,stop to output PWM;
			start<=result(0);
		--end if;
		elsif CS1_L='0' and LA="00010" and LWR_L='0' then--addr:10 write the Pusle Width:500~2500
		--if rising_edge(LCLK) then
			width<=result;
		--end if;
		elsif CS1_L='0' and LA="00010" and LRD_L='0' then--addr:10 read the Pusle Width;
		--if rising_edge(LCLK) then
			data<=width;
		end if;
	end if;
end process;
L2:process(start,LRST_L,CLK_1M)
begin	
	if start='1' then
		if rising_edge(CLK_1M) then
			if cycle="100111000011111" then
				width_start_flag<='1';
				cycle<="000000000000000";
			else 
				cycle<=cycle+1;
			end if;
			if width_start_flag='1' then
				if reg_width=width-1 then
					width_start_flag<='0';
			reg_width <="000000000000";
				else 
					reg_width<=reg_width+1;
				end if;
			end if;
		end if;
	else
		reg_width<="010111011100";
		cycle<="000000000000000";
		width_start_flag<='0';
	end if;	
end process;
PWM<=width_start_flag;
LRDYI_L<=GND;
LINT<=GND;
end rtl;