fre_ctrl.v

来自「verilog 经典例子的源码 非常适用于初学verilog的朋友们」· Verilog 代码 · 共 18 行

module fre_ctrl(clk,rst,count_en,count_clr,load);
output count_en,count_clr,load;
input clk,rst;
reg count_en,load;

always @(posedge clk)
  begin
	if(rst)
	 	begin  count_en=0;  load=1;  end
	else  	begin
	count_en=~count_en;
	load=~count_en;
	end
  end

assign  count_clr=~clk&load;
endmodule