代码搜索：conditional
找到约 2,177 项符合「conditional」的源代码
代码结果 2,177
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c gnu-cond-expr-2.c
/* Test diagnostic for GNU extension: omitting middle term of
conditional expression. Test with -pedantic. */
/* Origin: Joseph Myers */
/* { dg-do compile } */
/* { dg-
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c c99-array-lval-7.c
/* Test for non-lvalue arrays: test that C90 does not allow them in
conditional expressions, while in C99 they decay and are
allowed. */
/* Origin: Joseph Myers */
/* {
www.eeworm.com/read/153528/5649641
cs class1.cs
using System;
using System.Diagnostics;
namespace CondAttrib
{
class Thing
{
private string name;
public Thing(string name)
{
this.name = name;
#if DEBUG
SomeDebugFun
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vhd condsig.vhd
-- MAX+plus II VHDL Example
-- Conditional Signal Assignment
-- Copyright (c) 1994 Altera Corporation
ENTITY condsig IS
PORT
(
input0, input1, sel : IN BIT;
output : OUT BIT
);
E
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c krx21000.c
/*
Exercise 2-10. Rewrite the function lower, which converts upper case letters
to lower case, with a conditional expression instead of if-else.
Assumptions : by conditional expressi
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vhd 条件赋值：使用when else语句.vhd
-- Conditional Signal Assignment
-- download from: www.pld.com.cn & www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY condsig IS
PORT
(
input0, input1, sel : IN BI
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stats
Process : /bin/ls
Static Statistics
Total No. of Instructions = 14855 100%
Normal Instructions = 11692 78.708%
Conditional Jump = 1885 12.689%
Direct Jump = 316 2.127%
Indirect
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vhd condsig.vhd
-- MAX+plus II VHDL Example
-- Conditional Signal Assignment
-- Copyright (c) 1994 Altera Corporation
ENTITY condsig IS
PORT
(
input0, input1, sel : IN BIT;
output : OUT BIT
);
E