代码搜索：complex
找到约 10,000 项符合「complex」的源代码
代码结果 10,000
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v complex_bibus.v
module complex_bibus (clk, rst, sel1, sel2, sel3, data_bus, addr);
input clk, rst;
input sel1, sel2, sel3;
input [7:0] addr;
inout [7:0] data_bus;
wire [7:0] data_in;
reg [7:0] da
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prd complex_bibus.prd
#-- Synplicity, Inc.
#-- Version Synplify Pro 8.1
#-- Project file C:\prj\Example-5-1\complex_bibus\complex_bibus.prd
#-- Written on Mon Jan 02 21:43:55 2006
#
### Watch Implementation type ###
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prj complex_bibus.prj
#-- Synplicity, Inc.
#-- Version Synplify Pro 8.1
#-- Project file C:\prj\Example-5-1\complex_bibus\complex_bibus.prj
#-- Written on Mon Jan 02 21:43:55 2006
#add_file options
add_file -veril
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srs complex_bibus.srs
#
#
#
# Created by Synplify Verilog HDL Compiler version 3.1.0, Build 049R from Synplicity, Inc.
# Copyright 1994-2004 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Mon J
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fse complex_bibus.fse
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plg complex_bibus.plg
@P: Part : EP2C5QC208-6
@P: Worst Slack : NA
@P: complex_bibus Part : ep2c5qc208-6
@P: complex_bibus I/O ATOMs : 21
@P: complex_bibus DSP Blocks : 0 (0 nine bit DSP elements)
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msg complex_bibus.msg
@TM:1136208738
@N: FA174 :"":0:0:0:-1|The following device usage report estimates place and route data. Please look at the place and route report for final resource usage..
@N: MT195 :"":0:0:0:-1|Th
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vqm complex_bibus.vqm
//
// Written by Synplify
// Synplify 8.1.0, Build 539R.
// Mon Jan 02 21:43:57 2006
//
// Source file index table:
// Object locations will have the form :
// file 0 "noname"
// f
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tlg complex_bibus.tlg
Selecting top level module complex_bibus
@N:"C:\prj\Example-5-1\complex_bibus\decode.v":1:7:1:12|Synthesizing module decode
@N:"C:\prj\Example-5-1\complex_bibus\counter.v":2:7:2:13|Synthesizing mo
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tcl complex_bibus.tcl
# Run with quartus_sh -t
set_global_assignment -name ROOT "|complex_bibus"
set_global_assignment -name FAMILY "CYCLONE II"
set_global_assignment -name DEVICE "EP2C5Q208C6"
set_global_