complex_bibus.msg

设计与验证verilog hdl

@TM:1136208738
@N: FA174 :"":0:0:0:-1|The following device usage report estimates place and route data. Please look at the place and route report for final resource usage..
@N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
@N: MT204 :"":0:0:0:-1|Autoconstrain Mode is ON
@TM:1136209329
@N:  :"c:\prj\example-5-1\complex_bibus\complex_bibus2.v":1:7:1:19|Synthesizing module complex_bibus
@N:  :"c:\prj\example-5-1\complex_bibus\counter.v":2:7:2:13|Synthesizing module counter
@N:  :"c:\prj\example-5-1\complex_bibus\decode.v":1:7:1:12|Synthesizing module decode