complex_bibus.srs

设计与验证verilog hdl

#
#
#
# Created by Synplify Verilog HDL Compiler version 3.1.0, Build 049R from Synplicity, Inc.
# Copyright 1994-2004 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Mon Jan 02 21:43:56 2006
#
#
#OPTIONS:"|-fixsmult|-nram|-divnmod|-I|C:\\prj\\Example-5-1\\complex_bibus\\|-I|C:\\eda\\synplicity\\fpga_81\\lib|-v2001|-devicelib|C:\\eda\\synplicity\\fpga_81\\lib\\altera\\altera.v|-devicelib|C:\\eda\\synplicity\\fpga_81\\lib\\altera\\cycloneii.v|-devicelib|C:\\eda\\synplicity\\fpga_81\\lib\\altera\\altera_mf.v|-devicelib|C:\\eda\\synplicity\\fpga_81\\lib\\altera\\altera_lpm.v|-sm|-fid2|-sharing|off|-encrypt|-ui|-pro|-ram|-ll|2000"
#CUR:"C:\\eda\\synplicity\\fpga_81\\bin\\c_ver.exe":1115125636
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\altera\\altera.v":1046175234
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\altera\\altera.v":1046175234
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\altera\\cycloneii.v":1102487888
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\altera\\cycloneii.v":1102487888
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\altera\\altera_mf.v":1092812196
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\altera\\altera_mf.v":1092812196
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\altera\\altera_lpm.v":1111562108
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\altera\\altera_lpm.v":1111562108
#CUR:"C:\\prj\\Example-5-1\\complex_bibus\\counter.v":1136208124
#CUR:"C:\\prj\\Example-5-1\\complex_bibus\\counter.v":1136208124
#CUR:"C:\\prj\\Example-5-1\\complex_bibus\\decode.v":1136207518
#CUR:"C:\\prj\\Example-5-1\\complex_bibus\\decode.v":1136207518
#CUR:"C:\\prj\\Example-5-1\\complex_bibus\\complex_bibus.v":1136208930
#CUR:"C:\\prj\\Example-5-1\\complex_bibus\\complex_bibus.v":1136208930
f "C:\eda\synplicity\fpga_81\lib\altera\altera.v"; # file 0
af .is_verilog 1;
f "C:\eda\synplicity\fpga_81\lib\altera\cycloneii.v"; # file 1
af .is_verilog 1;
f "C:\eda\synplicity\fpga_81\lib\altera\altera_mf.v"; # file 2
af .is_verilog 1;
f "C:\eda\synplicity\fpga_81\lib\altera\altera_lpm.v"; # file 3
af .is_verilog 1;
f "C:\prj\Example-5-1\complex_bibus\counter.v"; # file 4
af .is_verilog 1;
f "C:\prj\Example-5-1\complex_bibus\decode.v"; # file 5
af .is_verilog 1;
f "C:\prj\Example-5-1\complex_bibus\complex_bibus.v"; # file 6
af .is_verilog 1;
@E
@ 
ftell;
@E@MR@46::4(::R4.I	FsRO8CFR8CPHCsD;Fo
RNP3PH#CDsHF4oR;P
NR#3H_sPCHoDFR
4;N3PRFosHhCNlRC"8OCF8"
;

@HR@d6:::4.dn:4RFODOO	RD	FO;



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RRRR4kM_8N8sk_L#9rjR4kM_8N8sk_L#9r4R4kM_8N8sk_L#9r.R4kM_8N8sk_L#9rd
RRRR4kM_8N8sk_L#9rcR4kM_8N8sk_L#9rn;R
b@:@644n:jn:4:R.4HRMPk_M48NN0_#Lk_0Fk4kURM84_N_0NL_k#F4k0UNR80LN_kF#_kU04;R
b@:@644(:j(:4:R.4HRMPk_M48NN0_#Lk_0Fk4kgRM84_N_0NL_k#F4k0gNR80LN_kF#_kg04;R
b@:@644U:jU:4:R.4HRMPk_M48NN0_#Lk_0Fk.kjRM84_N_0NL_k#F.k0jNR80LN_kF#_kj0.;R
b@:@64j4:::446MRN8kPRM84_N_0NL_k#F.k0jR_4k_M48NN0_#Lk_0Fk.4j_R4kM_08NNk_L#k_F0
.jRRRRk_M48NN0_#Lk_0Fk4kgRM84_N_0NL_k#F4k0Ub;
R6@@::46g6:4:R4.bGlkR08NNk_L#k_F0r_((9:jR08NNk_L#k_F0r_((9:jRDVN#VC,NCD#,DVN#VC,NCD#,k0sCs,0k0C,s,kC0Csk,08NNk_L#k_F0
4URRRR0Csk,k0sCs,0k0C,s,kCV#NDCN,VD,#CV#NDCN,VD,#C8NN0_#Lk_0Fk40gRs,kC0Csk,k0sCs,0k0C,s,kC0Csk,k0sCs,0k8C,N_0NL_k#F.k0jR
RRNR80LN_kH#_M:r(jk9,M84_N_0NL_k#F.k0j;_4
@bR@46:4::j464:RV8VsNR80LN_kF#_k(0r:Rj98NN0_#Lk_0Fkrj(:9NR80LN_kF#_k(0_rj(:9R
RRDROFRO	sCC#0N;
H#R3$bM_sMFONRlC"FbsON_80LN_kF#_k;0"
RNH3Ds0_HFsolMNC8R"N_0NL_k#F"k0;-
y--------------------------------- 
@
ftell;
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y--------------------------------- 
@
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Rn@@:4d:.::d4H6RMkPRM#4_CRD4k_M4#4CDRD#C4b;
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