代码搜索：buffer
找到约 10,000 项符合「buffer」的源代码
代码结果 10,000
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vhd buffer_img.vhd
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-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation,
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xcp buffer_comp.xcp
# Xilinx CORE Generator 6.1i
SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0
CSET primitive_selection = Optimize_For_Area
CSET init_value = 0
CSET register_inputs = false
CSET write_enable_po
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vhd buffer_comp.vhd
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-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation,
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edn buffer_comp.edn
(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2004 10 9 1 3 47)
(author "Xilinx, Inc.")
(program "Xilinx CORE Generator" (version "Xilinx
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vho buffer_comp.vho
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-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation,
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vbe buffer0.vbe
ENTITY buffer0 IS
PORT (
bo1 : IN BIT;
bo2 : OUT BIT
);
END buffer0;
ARCHITECTURE buf0_arch OF buffer0 IS
BEGIN
with bo1 select
bo2
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pat buffer1.pat
in bu1 B;
out bu2 B;
begin
pat_0 : 0 ?0;
pat_1 : 1 ?0;
end;
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vbe buffer1.vbe
ENTITY buffer1 IS
PORT (
bu1 : IN BIT;
bu2 : OUT BIT
);
END buffer1;
ARCHITECTURE buf1_arch OF buffer1 IS
BEGIN
with bu1 select
bu2
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pat buffer0.pat
in bo1 B;
out bo2 B;
begin
pat_0 : 0 ?0;
pat_1 : 1 ?0;
end;
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coe buffer_img.coe
MEMORY_INITIALIZATION_RADIX=16;
MEMORY_INITIALIZATION_VECTOR=
FF,D8,FF,E0,00,10,4A,46,49,46,00,01,02,00,00,01,00,01,00,00,FF,C0,00,11,08,
00,00,00,00,
03,01,22,00,02,11,01,03,11,01,FF,DB,00,84,
00,