buffer0.vbe

i need of vhdl code for 32-bit risc processor

ENTITY buffer0 IS
PORT (
bo1 : IN BIT;
bo2 : OUT BIT
);
END buffer0;

ARCHITECTURE buf0_arch OF buffer0 IS

BEGIN
with bo1 select
bo2 <= b"0" when b"1",
       b"0" when b"0" ;
END;