代码搜索：asynchronous
找到约 2,366 项符合「asynchronous」的源代码
代码结果 2,366
www.eeworm.com/read/476030/6772701
vhd reginf.vhd
-- MAX+plus II VHDL Example
-- Register Inference
-- Copyright (c) 1994 Altera Corporation
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load, data : IN BIT;
q1, q2, q3, q4, q5, q6, q7 : O
www.eeworm.com/read/370579/9595105
vhd 带load、clr等功能的寄存器.vhd
-- Register Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load, data : IN BIT;
q1, q2,
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v reg4_nbp.v
//--------------------------------------------------
//4-bit register for Non-blocking Procedural Assignment
//Filename : reg_nbp.v
//--------------------------------------------------
module reg4
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v counter_sim.v
//--------------------------------------------------
// 8-bit synchronous counter wit asynchronous reset
// Filename : counter_sim.v
//--------------------------------------------------
module coun
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inc 80386ex.inc
;
; 80386EX Register definitions
;
; Define Macro for accessing the 80386EX registers. Using these macros
; allows a user to move between high and low I/O space easily.
%*DEFINE(SetEXRegWord (r
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vhd 带load、clr等功能的寄存器.vhd
-- Register Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load, data : IN BIT;
q1, q2,
www.eeworm.com/read/415351/11075594
vhd 带load、clr等功能的寄存器.vhd
-- Register Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load, data : IN BIT;
q1, q2,
www.eeworm.com/read/415056/11084910
c emif.c
void initial_emif(void)
{
int i;
*EBSR=0x0201; //Parallel Port Mode:Full EMIF Mode
*EMI_RST=0x00; //复位EMIF状态机并等待100个周期
for(i=0;i
www.eeworm.com/read/148107/12493744
asm cvectors.asm
* Writing to the C2xx Asynchronous Serial Port in C V1.00
* by Jeff Axelrod 3/26/97
.title "vectors.asm"
.ref _c_int0,_nothing,_uart
.sect ".vectors"
reset: b _c_int0
int1: b _nothing
i
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vhd reginf.vhd
-- MAX+plus II VHDL Example
-- Register Inference
-- Copyright (c) 1994 Altera Corporation
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load, data : IN BIT;
q1, q2, q3, q4, q5, q6, q7 : O