counter_sim.v

来自「FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节」· Verilog 代码 · 共 19 行

//--------------------------------------------------
// 8-bit synchronous counter wit asynchronous reset
// Filename : counter_sim.v
//--------------------------------------------------
module counter_sim(CLK, RESET, COUNT);
    input CLK;
    input RESET;
    output [7:0] COUNT;
    reg [7:0] COUNT;
 
always @(posedge CLK or posedge RESET)
begin
   if (RESET)
      COUNT <= 8'b0;
   else 
      COUNT <= COUNT + 1;
end
endmodule