代码搜索：adder
找到约 6,792 项符合「adder」的源代码
代码结果 6,792
www.eeworm.com/read/370579/9595087
txt 加法器：generate语句的应用.txt
-- n-bit Adder using the Generate Statement
-- download from: www.fpga.com.cn & www.pld.com.cn
library IEEE;
use IEEE.Std_logic_1164.all;
ENTITY addn IS
GENERIC(n : POSITIVE := 3); --no.
www.eeworm.com/read/109067/15565308
v dw01_add.v
//
// S.Arvind
// 02/02/99
// Ripple adder
//
module DW01_add (A, B, CI, SUM, CO);
parameter width = 32;
input [width-1:0] A, B;
input CI;
output [width-1:0] SUM;
o
www.eeworm.com/read/384430/8869636
v csa_mult_8m24.v
// This is a program of Carry Save Adder Multiplier.
`timescale 1ns/1ps
module csa_mult_8m24(a,b,product);
input [23:0] a; // 24bit
input [7:0] b; // 8bit
// input
www.eeworm.com/read/377553/9271628
vhd bcd_add_sub.vhd
--bcd_add_sub.vhd 3 digits bcd adder/subtractor with start and done
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd_add_sub is
port(
clock : in std_logic ;--
www.eeworm.com/read/377553/9271655
vhd bcd3.vhd
--bcd3.vhd 3 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd3 is
port(
a : in std_logic_vector(11 downto 0);--砆
www.eeworm.com/read/164942/10081176
vhd bcd_add_sub.vhd
--bcd_add_sub.vhd 3 digits bcd adder/subtractor with start and done
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd_add_sub is
port(
clock : in std_logic ;--
www.eeworm.com/read/164942/10081206
vhd bcd3.vhd
--bcd3.vhd 3 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd3 is
port(
a : in std_logic_vector(11 downto 0);--砆
www.eeworm.com/read/275690/10801123
vhd bcd_add_sub.vhd
--bcd_add_sub.vhd 3 digits bcd adder/subtractor with start and done
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd_add_sub is
port(
clock : in std_logic ;--
www.eeworm.com/read/275690/10801409
vhd bcd3.vhd
--bcd3.vhd 3 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd3 is
port(
a : in std_logic_vector(11 downto 0);--砆
www.eeworm.com/read/274276/10879368
vhd bcd_add_sub.vhd
--bcd_add_sub.vhd 3 digits bcd adder/subtractor with start and done
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd_add_sub is
port(
clock : in std_logic ;--