dw01_add.v

RISC的指令VerilogHDL实现

//
//  S.Arvind 
//  02/02/99
//  Ripple adder 
//

module DW01_add (A, B, CI, SUM, CO);

  parameter width = 32;
 
  input  [width-1:0] A, B;
  input  CI;
  output [width-1:0] SUM;
  output CO;
 
  reg [width:0] C;       // carry
  integer i;
 
  assign CO  = C[width];
  assign SUM = A ^ B ^ C[width-1:0];
 
  always @ (A or B or CI)
    begin
      C[0] = CI;
      for (i=1; i <= width; i=i+1)
        C[i] = (A[i-1] & B[i-1]) | (C[i-1] & (A[i-1] | B[i-1]));
    end
 
endmodule