csa_mult_8m24.v

新型的浮点乘法器 用csa来实现可以用在浮点乘法器的地方

// This is a program of Carry Save Adder Multiplier.
`timescale 1ns/1ps
module csa_mult_8m24(a,b,product);
  input [23:0] a;            // 24bit
  input [7:0] b;             // 8bit
//  input       clk, rst_n;
  output[31:0] product;
  
  wire [24:0] a_double = {a,1'b0}; // 2*a
  wire [25:0] a_triple = a_double + a; // 3*a
  
  wire [1:0] sel01 = {b[1],b[0]};
  wire [1:0] sel23 = {b[3],b[2]};
  wire [1:0] sel45 = {b[5],b[4]};
  wire [1:0] sel67 = {b[7],b[6]};
  
  wire [29:0] a_in = (sel01==2'b00)?0:(sel01==2'b01)?{6'b0,a}:
                     (sel01==2'b10)?{5'b0,a_double}:(sel01==2'b11)?{4'b0,a_triple}:0;
   
  wire [27:0] b_in = (sel23==2'b00)?0:(sel23==2'b01)?{4'b0,a}:
                     (sel23==2'b10)?{3'b0,a_double}:(sel23==2'b11)?{2'b0,a_triple}:0;
  
  wire [29:0] b_inx = {b_in,2'b0};
  
  wire [25:0]  c_in = (sel45==2'b00)?0:(sel45==2'b01)?{2'b0,a}:
                     (sel45==2'b10)?{1'b0,a_double}:(sel45==2'b11)?a_triple:0;
                     
  wire [29:0] c_inx = {c_in,4'b0};
  
  wire [25:0]  d_in = (sel67==2'b00)?0:(sel67==2'b01)?{2'b0,a}:
                     (sel67==2'b10)?{1'b0,a_double}:(sel67==2'b11)?a_triple:0;
  
  wire [31:0] d_inx = {d_in,6'b0};
  wire [29:0] s1_o,c1_o;
  wire [31:0] s2_o,c2_o;
  
  csa3_30 csa3_30(.a1(a_in),.a2(b_inx),.a3(c_inx),.s(s1_o),.c(c1_o));//.clk(clk),.rst_n(rst_n)
  
  csa3_32 csa3_32(.a1({2'b0,s1_o}),.a2({1'b0,c1_o,1'b0}),.a3(d_inx),.s(s2_o),.c(c2_o));
  
  assign product = s2_o + {c2_o,1'b0};
 
endmodule

//===================================================================================
`define width1 30

module csa3_30(a1,a2,a3,s,c);
  input [`width1-1:0] a1,a2,a3;
  output[`width1-1:0] s,c;
  
  assign s = a1^a2^a3;
  assign c = (a1&a2)|(a2&a3)|(a1&a3);
endmodule


//====================================================================================
`define width2 32

module csa3_32(a1,a2,a3,s,c);
  input [`width2-1:0] a1,a2,a3;
  output[`width2-1:0] s,c;
  
  assign s = a1^a2^a3;
  assign c = (a1&a2)|(a2&a3)|(a1&a3);
endmodule