代码搜索：adder

找到约 6,792 项符合「adder」的源代码

代码结果 6,792
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/324587/6284578

rpt mux16.rpt

Project Information e:\cal\mux16.rpt MAX+plus II Compiler Report File Version 10.2 07/10/2002 Compiled: 06/27/2007 12:04:54 Copyright (C) 1988-2002 Al
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www.eeworm.com/read/177969/6312464

rpt hour.sim.rpt

Simulator report for hour Tue Oct 28 17:08:46 2008 Version 5.1 Build 176 10/26/2005 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2.
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www.eeworm.com/read/177969/6312477

rpt second.sim.rpt

Simulator report for second Tue Oct 28 16:55:18 2008 Version 5.1 Build 176 10/26/2005 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2
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www.eeworm.com/read/177969/6312530

rpt minute.sim.rpt

Simulator report for minute Tue Oct 28 17:03:26 2008 Version 5.1 Build 176 10/26/2005 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2
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www.eeworm.com/read/492914/6413856

txt 全加器仿真程序.txt

全加器仿真程序。 LIBRARY IEEE; USE STD_TEXTIO.ALL; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_TEXTIO.ALL; ENTITY test_fadder IS END ENTITY test_fadder; ARCHITECTURE arc2 OF test_fadde
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www.eeworm.com/read/477872/6724974

hif cpsk.hif

HIF003 -- -- Copyright (C) 1988-2000 Altera Corporation -- Any megafunction design, and related net list (encrypted or decrypted), -- support information, device programming or simulation file, an
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www.eeworm.com/read/400964/11566536

vhd alu.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; LIBRARY LPM; USE LPM.LPM_COMPONENTS.ALL; ENTITY ALU IS GENERIC (width:NATURAL:=7; op_w:NATURAL:=2); PORT ( a, b : IN std_logic_vector
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www.eeworm.com/read/261127/11665453

rpt hour.rpt

Project Information e:\kai\timer\hour.rpt MAX+plus II Compiler Report File Version 9.23 3/19/99 Compiled: 05/16/2007 20:57:19 Copyright (C) 1988-1999 Alter
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www.eeworm.com/read/155384/11881426

xrf ryxiangwei_modelsim.xrf

vendor_name = ModelSim source_file = 1, ryxiangwei.v source_file = 1, h:/quartus/libraries/megafunctions/lpm_add_sub.tdf source_file = 1, h:/quartus/libraries/megafunctions/addcore.inc source_file
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www.eeworm.com/read/342532/12013120

eqn second_pulse_latch.map.eqn

--C3L71 is lpm_add_sub:add_rtl_0|addcore:adder[1]|prop_node[3]~100 C3L71_p1_out = A1L15Q & A1L94Q; C3L71_p2_out = A1L15Q & !acceleration[13]; C3L71_p3_out = A1L94Q & !acceleration[14]; C3L71_p4_ou
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