代码搜索：adder
找到约 6,792 项符合「adder」的源代码
代码结果 6,792
www.eeworm.com/read/339662/12212046
vhd dds_dds.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
ENTITY dds_dds IS
port(ftw: in std_logic_vector(23 downto 0); --频率控制字
clk: in
www.eeworm.com/read/339411/12237545
qsf ch_fir.qsf
# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
www.eeworm.com/read/222378/14693952
vqm dds.vqm
// Copyright (C) 1991-2004 Altera Corporation
// Any megafunction design, and related netlist (encrypted or decrypted),
// support information, device programming or simulation file, and any
www.eeworm.com/read/117979/14891638
fit alu.fit
-- MAX+plus II Compiler Fit File
-- Version 10.0 9/14/2000
-- Compiled: 12/01/2004 11:26:49
-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and
www.eeworm.com/read/213084/15142941
transcript
# Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl
# do TB_Pipeline_Adder.fdo
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE III vcom 6.0d Compiler 2005
www.eeworm.com/read/211745/15174687
vhd dds_dds.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
ENTITY dds_dds IS
port(ftw: in std_logic_vector(23 downto 0); --频率控制字
clk: in
www.eeworm.com/read/395400/8180297
rpt singt.sim.rpt
Simulator report for singt
Tue Dec 12 08:42:02 2000
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Leg
www.eeworm.com/read/394007/8251222
vhd f_fadd.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity f_fadd is
Port ( A : in STD_LOGIC_VECTOR(0 to 3);
B : in S
www.eeworm.com/read/394007/8251382
vhd lcdf_fadd.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lcdf_fadd is
Port ( A : in STD_LOGIC_VECTOR(0 to 3);
B : in
www.eeworm.com/read/367436/9748719
vhd dds_dds.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
ENTITY dds_dds IS
port(ftw: in std_logic_vector(23 downto 0); --频率控制字
clk: in