dds.vqm

DDS的DSP实现

// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
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// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
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// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version"

// DATE "08/11/2004 17:17:50"

module 	dds (
	clock,
	sclrp,
	iAMPlifys,
	iFREQWORDs,
	oDA_CSs,
	oDA_DATAs);
input 	clock;
input 	sclrp;
input 	[7:0] iAMPlifys;
input 	[7:0] iFREQWORDs;
output 	oDA_CSs;
output 	[7:0] oDA_DATAs;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[21] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[20] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[19] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[18] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[17] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[16] ;
wire \SubDDS:SubDDSi|SRED:BusConversion2i|AROUND:grnd_ur|lpm_add_sub:i_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[15] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[9] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[8] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ;
wire \SubDDS:SubDDSi|SRED:BusConversion3i|AROUND:grnd_ur|lpm_add_sub:i_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|right_bit[8]~117_1 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|right_bit[7]~118_1 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|right_bit[6]~119_1 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|right_bit[5]~120_1 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|right_bit[4]~121_1 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|right_bit[3]~122_1 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[2]|right_bit[8]~117_1 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[2]|right_bit[7]~118_1 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[2]|right_bit[6]~119_1 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[1]|right_bit[8]~117_1 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|right_bit[2]~123_1 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[2]|right_bit[5]~120_1 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[1]|right_bit[7]~118_1 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|right_bit[1]~124_1 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[2]|right_bit[4]~121_1 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[1]|right_bit[6]~119_1 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[3]|right_bit[0]~125_1 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[2]|right_bit[3]~122_1 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[1]|right_bit[5]~120_1 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[2]|right_bit[2]~123_1 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[1]|right_bit[4]~121_1 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[2]|right_bit[1]~124_1 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[1]|right_bit[3]~122_1 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[2]|right_bit[0]~125_1 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[1]|right_bit[2]~123_1 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[1]|right_bit[1]~124_1 ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|lpm_mult:glpm_pipe_L|multcore:mult_core|mul_lfrg:mul_lfrg_mid_mod[1]|right_bit[0]~125_1 ;
wire \sclrp~dataout ;
wire \iAMPlifys[7]~dataout ;
wire \clock~dataout ;
wire \SubDDS:SubDDSi|AltiMult:Product1i|databint[7] ;
wire \iFREQWORDs[7]~dataout ;
wire \SubDDS:SubDDSi|SDelay:Delayi|result[22]~reg0 ;
wire \iFREQWORDs[6]~dataout ;
wire \SubDDS:SubDDSi|SDelay:Delayi|result[21]~reg0 ;
wire \iFREQWORDs[5]~dataout ;
wire \SubDDS:SubDDSi|SDelay:Delayi|result[20]~reg0 ;
wire \iFREQWORDs[4]~dataout ;
wire \SubDDS:SubDDSi|SDelay:Delayi|result[19]~reg0 ;
wire \iFREQWORDs[3]~dataout ;
wire \SubDDS:SubDDSi|SDelay:Delayi|result[18]~reg0 ;
wire \iFREQWORDs[2]~dataout ;
wire \SubDDS:SubDDSi|SDelay:Delayi|result[17]~reg0 ;
wire \iFREQWORDs[1]~dataout ;
wire \SubDDS:SubDDSi|SDelay:Delayi|result[16]~reg0 ;
wire \iFREQWORDs[0]~dataout ;
wire \SubDDS:SubDDSi|SDelay:Delayi|result[15]~reg0 ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|result[15]~reg0 ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[0] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|result[16]~reg0 ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[1] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|result[17]~reg0 ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[2] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|result[18]~reg0 ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[3] ;
wire \SubDDS:SubDDSi|SAdderSub:u9|lpm_add_sub:i_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ;