代码搜索：adder
找到约 6,792 项符合「adder」的源代码
代码结果 6,792
www.eeworm.com/read/423108/10586630
pin adder.pin
-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
www.eeworm.com/read/423108/10586668
sof adder.sof
www.eeworm.com/read/159869/10605825
v adder.v
module adder(cout,sum,a,b,cin);
parameter size=16;
output cout;
output[size-1:0] sum;
input cin;
input[size-1:0] a,b;
assign {cout,sum}=a+b+cin;
endmodule
www.eeworm.com/read/422532/10631558
vhd adder.vhd
-- MAX+plus II VHDL Example
-- Conversion Function
-- Copyright (c) 1994 Altera Corporation
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY adder IS
PORT (o
www.eeworm.com/read/159552/10640244
v adder.v
module adder(cout,sum,a,b,cin);
parameter size=16;
output cout;
output[size-1:0] sum;
input cin;
input[size-1:0] a,b;
assign {cout,sum}=a+b+cin;
endmodule
www.eeworm.com/read/422113/10663098
v adder.v
//
// Verilog Module dwt2_lib.adder.arch_name
//
// Created:
// by - VLSI4.UNKNOWN (VLSI04)
// at - 11:09:16 03/21/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12
www.eeworm.com/read/159105/10694704
vhd adder.vhd
-- MAX+plus II VHDL Example
-- Conversion Function
-- Copyright (c) 1994 Altera Corporation
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY adder IS
PORT (o
www.eeworm.com/read/349226/10840482
lif adder.lif
#Life 1.05
#D Binary Adder
#D By David Buckingham, with size optimization by Mark
#D Niemec, 1975. Two glider streams enter the lower
#D right, representing the binary numbers 1110 and 0011.
#D
www.eeworm.com/read/418677/10936159
v adder.v
// megafunction wizard: %LPM_ADD_SUB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_add_sub
// ============================================================
// File Name: adder.v
//
www.eeworm.com/read/467448/7012807
vhd adder.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(load: in std_logic;
a:in std_logic_vector(15 downto 0);
b:in std_logic_vector(15