adder.v

it is used to find traffic

//
// Verilog Module dwt2_lib.adder.arch_name
//
// Created:
//          by - VLSI4.UNKNOWN (VLSI04)
//          at - 11:09:16 03/21/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
//
`resetall
`timescale 1ns/10ps
module adder(in1,in2,out) ; //in1,in2 are in twos complement representation
 input [23:0] in1,in2;
 output [23:0] out;
 reg [23:0] out;
 wire [23:0] out_sum;
 wire out_carry;
 wire check;
 reg [23:0] in1_t,in2_t;
 
 assign check=in1[23] ^ in2[23];
 
always@(in1 or in2)
begin
  if((in1[23]==1'b1) && (in2[23]==1'b1))
  begin
    in1_t=~in1+1'b1;
    in2_t=~in2+1'b1;
    //out=~out_sum+1'b1;
  end
  else
  begin
     in1_t=in1;
     in2_t=in2;
     //if(check==1'b1)
//     begin
//      if(out_carry==1'b1)
//      out=out_sum;
//      else
//      out=~out_sum+1'b1;
//     end
//     else
//     out=out_sum;
  end
  
end
always@(out_sum)
begin
  if((in1[23]==1'b1) && (in2[23]==1'b1))
     out=~out_sum+1'b1;
  else
  begin
    if(check==1'b1)
     begin
      if(out_carry==1'b1)
      out=out_sum;
      else
      out=~out_sum+1'b1;
     end
     else
     out=out_sum;
  end
 end



cla_24 add1(in1_t,in2_t,out_sum,out_carry);

// ### Please start your Verilog code here ###
endmodule