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main.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Qua
stop_watch.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity hdl_demo is
port(
rst : in vl_logic;
clk : in vl_logic;
start_value : in vl_logic_
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity hdl_demo is
port(
rst : in vl_logic;
clk : in vl_logic;
start_value : in vl_logic_
design_spec_ao.dc
###############################################################################
#
# Design Specification
#
# Author: Rudolf Usselmann
# rudi@asics.ws
#
# Revision:
# 5/10/01 RU Initial Sript
#
design_spec_po.dc
###############################################################################
#
# Design Specification
#
# Author: Rudolf Usselmann
# rudi@asics.ws
#
# Revision:
# 5/10/01 RU Initial Sript
#
uart_txd.hif
Version 9.0 Build 132 02/25/2009 SJ Full Version
11
910
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libra
i2c.npl
JDF G
// Created by Project Navigator ver 1.0
PROJECT I2C
DESIGN i2c
DEVFAM spartan2e
DEVFAMTIME 0
DEVICE xc2s50e
DEVICETIME 0
DEVPKG tq144
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLE
i2c.gfl
# XST (Creating Lso File) :
i2c_master_top.lso
# Check Syntax
i2c_master_top.stx
# XST (Creating Lso File) :
i2c_master_bit_ctrl.lso
# Check Syntax
i2c_master_bit_ctrl.stx
# xst flow : RunXS
meta.yml
# http://module-build.sourceforge.net/META-spec.html
name: Verilog-Perl
version: 3.120
version_from: Language.pm
license: perl
installdirs: site
requires:
Pod::Usage: