design_spec_po.dc

来自「des加密算法的verilog语言的实现」· DC 代码 · 共 27 行

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# Design Specification
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# Author: Rudolf Usselmann
#         [e-mail]
#
# Revision:
# 5/10/01 RU Initial Sript
#
#
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# ==============================================
# Setup Design Parameters

set design_files {sbox2 sbox4 sbox6 sbox8 sbox1 sbox3 sbox5 sbox7 crp key_sel des}

set design_name des
set active_design des
 
# Next Statement defines all clocks and resets in the design
set special_net {clk}
 
set hdl_src_dir {../../rtl/verilog/common ../../rtl/verilog/perf_opt}