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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity can_register is
generic(
width : integer := 8
);
port(
data_in : in vl_logic_vector;
data_ou
i2c.gfl
# XST (Creating Lso File) :
i2c_master_top.lso
# Check Syntax
i2c_master_top.stx
# XST (Creating Lso File) :
i2c_master_bit_ctrl.lso
# Check Syntax
i2c_master_bit_ctrl.stx
# xst flow : RunXS
hghm.tbw
version 3
C:/rahul/fulladder2/fa.v
fa
VERILOG
VERILOG
C:/rahul/fulladder2/hghm.xwv
Clocked
-
-
1000000000
ns
GSR:true
PRLD:false
100000000
CLOCK_LIST_BEGIN
a
100000000
100000000
1500
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity fft64 is
port(
sclr : in vl_logic;
ce : in vl_logic;
fwd_inv_we : in vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity fft_fun is
generic(
VCC : integer := 1;
GND : integer := 0
);
port(
din_re : in
i2c.npl
JDF G
// Created by Project Navigator ver 1.0
PROJECT I2C
DESIGN i2c
DEVFAM spartan2e
DEVFAMTIME 0
DEVICE xc2s50e
DEVICETIME 0
DEVPKG tq144
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLE
i2c.gfl
# XST (Creating Lso File) :
i2c_master_top.lso
# Check Syntax
i2c_master_top.stx
# XST (Creating Lso File) :
i2c_master_bit_ctrl.lso
# Check Syntax
i2c_master_bit_ctrl.stx
# xst flow : RunXS
i2c.npl
JDF G
// Created by Project Navigator ver 1.0
PROJECT I2C
DESIGN i2c
DEVFAM spartan2e
DEVFAMTIME 0
DEVICE xc2s50e
DEVICETIME 0
DEVPKG tq144
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLE
i2c.gfl
# XST (Creating Lso File) :
i2c_master_top.lso
# Check Syntax
i2c_master_top.stx
# XST (Creating Lso File) :
i2c_master_bit_ctrl.lso
# Check Syntax
i2c_master_bit_ctrl.stx
# xst flow : RunXS
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_mac_out_internal is
generic(
operation_mode : string := "output_only";
dataa_width : integer := 36;
datab_wi