_primary.vhd

来自「调用FPGA的IP核实现FFT运算」· VHDL 代码 · 共 26 行

library verilog;
use verilog.vl_types.all;
entity fft64 is
    port(
        sclr            : in     vl_logic;
        ce              : in     vl_logic;
        fwd_inv_we      : in     vl_logic;
        rfd             : out    vl_logic;
        start           : in     vl_logic;
        fwd_inv         : in     vl_logic;
        dv              : out    vl_logic;
        unload          : in     vl_logic;
        done            : out    vl_logic;
        clk             : in     vl_logic;
        busy            : out    vl_logic;
        edone           : out    vl_logic;
        xn_re           : in     vl_logic_vector(7 downto 0);
        blk_exp         : out    vl_logic_vector(4 downto 0);
        xk_im           : out    vl_logic_vector(7 downto 0);
        xn_index        : out    vl_logic_vector(5 downto 0);
        xk_re           : out    vl_logic_vector(7 downto 0);
        xn_im           : in     vl_logic_vector(7 downto 0);
        xk_index        : out    vl_logic_vector(5 downto 0)
    );
end fft64;