_primary.vhd

来自「调用FPGA的IP核实现FFT运算」· VHDL 代码 · 共 20 行

library verilog;
use verilog.vl_types.all;
entity fft_fun is
    generic(
        VCC             : integer := 1;
        GND             : integer := 0
    );
    port(
        din_re          : in     vl_logic_vector(7 downto 0);
        din_im          : in     vl_logic_vector(7 downto 0);
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        data_load_start : in     vl_logic;
        dout_re         : out    vl_logic_vector(7 downto 0);
        dout_im         : out    vl_logic_vector(7 downto 0);
        blk             : out    vl_logic_vector(4 downto 0);
        data_valid      : out    vl_logic
    );
end fft_fun;