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Verilog 的代码
se_pa.tap
n work se_pa verilog;
gi pa_out[3:0];
ai .slack_logic 997.000 ;
gp Q[0];
ap .slack_logic 997.000 ;
gp Q[1];
ap .slack_logic 997.000 ;
gp Q[2];
ap .slack_logic 997.000 ;
gp Q[3];
ap .slac
mult_tst.vif
#
# Synplicity Verification Interface File
# Generated using Synplify-pro
#
# Copyright (c) 1996-2005 Synplicity, Inc.
# All rights reserved
#
# Set logfile options
vif_set_result_file Mult
mult_tst.vif
#
# Synplicity Verification Interface File
# Generated using Synplify-pro
#
# Copyright (c) 1996-2005 Synplicity, Inc.
# All rights reserved
#
# Set logfile options
vif_set_result_file Mult
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity song is
port(
clk : in vl_logic;
speaker : out vl_logic;
index : in vl_logic_vect
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ddr_data_path is
port(
clk100 : in vl_logic;
clk200 : in vl_logic;
reset_n : in vl_l
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity counter16 is
port(
reset_n : in vl_logic;
clk_in : in vl_logic;
clk16_out : out vl_logic
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity nand3b2 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i0
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibufg_hstl_iii is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ibuf_hstl_iv is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity obuft_lvttl_f_4 is
generic(
cds_action : string := "ignore"
);
port(
o : out vl_logic;
i