_primary.vhd

风格非常好 一六位计数器 无密码 质量很高

library verilog;
use verilog.vl_types.all;
entity counter16 is
    port(
        reset_n         : in     vl_logic;
        clk_in          : in     vl_logic;
        clk16_out       : out    vl_logic_vector(15 downto 0)
    );
end counter16;