_primary.vhd

来自「这是一个FPGA的实验源码」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity song is
    port(
        clk             : in     vl_logic;
        speaker         : out    vl_logic;
        index           : in     vl_logic_vector(2 downto 0);
        seg             : out    vl_logic_vector(6 downto 0);
        seg_scan        : out    vl_logic_vector(2 downto 0)
    );
end song;