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Verilog 的代码
trafficlight.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Qua
flip_latch.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
iir.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: iir.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//***************************************************
iir.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: iir.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//***************************************************
iir.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: iir.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//***************************************************
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity comparator is
port(
x : in vl_logic_vector(31 downto 0);
y : in vl_logic_vector(31 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity SDRAM_model_AVL is
port(
Addr : in vl_logic_vector(31 downto 0);
Data : inout vl_logic_vector(31 downto
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity SDRAM_model_simple is
port(
Addr : in vl_logic_vector(31 downto 0);
Data : inout vl_logic_vector(31 dow
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity wb_master_model is
generic(
dwidth : integer := 32;
awidth : integer := 32
);
port(
clk
_info
m255
cModel Technology
dE:\刘韬\MY_WORK\FPGA\程序\I2C
vglbl
I;3bdO6U;R_i?oXm0zZ=6m3
V]6_PH00iDgcD`AVz9`gA:0
w1059855545
FC:/Program Files/Xilinx/verilog/src/glbl.v
L0 5
OE;L;5.7e;17
r1
31
vi2c_slave_model