_primary.vhd

来自「ARM10 INSTALALTION GUIDE」· VHDL 代码 · 共 16 行

library verilog;
use verilog.vl_types.all;
entity SDRAM_model_AVL is
    port(
        Addr            : in     vl_logic_vector(31 downto 0);
        Data            : inout  vl_logic_vector(31 downto 0);
        nRAS            : in     vl_logic;
        nCAS            : in     vl_logic;
        nWE             : in     vl_logic;
        SEQ             : in     vl_logic;
        nCS             : in     vl_logic;
        MCLK            : in     vl_logic;
        BYTE            : in     vl_logic
    );
end SDRAM_model_AVL;