_primary.vhd

SPI 总线协议源码SPI 总线协议源码SPI 总线协议源码

library verilog;
use verilog.vl_types.all;
entity wb_master_model is
    generic(
        dwidth          : integer := 32;
        awidth          : integer := 32
    );
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        adr             : out    vl_logic_vector;
        din             : in     vl_logic_vector;
        dout            : out    vl_logic_vector;
        cyc             : out    vl_logic;
        stb             : out    vl_logic;
        we              : out    vl_logic;
        sel             : out    vl_logic_vector;
        ack             : in     vl_logic;
        err             : in     vl_logic;
        rty             : in     vl_logic
    );
end wb_master_model;