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library verilog; use verilog.vl_types.all; entity fir_asr is port( addr : in vl_logic_vector(7 downto 0); d : in vl_logic_vector(11 downto 0);

library verilog; use verilog.vl_types.all; entity stratix_io is generic( operation_mode : string := "input"; ddio_mode : string := "none"; open_drain_output: strin

library verilog; use verilog.vl_types.all; entity b5mux21 is port( mo : out vl_logic_vector(4 downto 0); a : in vl_logic_vector(4 downto 0);

library verilog; use verilog.vl_types.all; entity stratix_ram_internal is generic( operation_mode : string := "single_port"; ram_block_type : string := "M512"; mixed_po

library verilog; use verilog.vl_types.all; entity leg is port( d_irq : in vl_logic_vector(1 downto 0); d_re : out vl_logic; d_we : ou

library verilog; use verilog.vl_types.all; entity pll1 is port( inclock : in vl_logic; locked : out vl_logic; clock0 : out vl_logic;

library verilog; use verilog.vl_types.all; entity ddr_sdram is port( clk : in vl_logic; reset_n : in vl_logic; addr : in vl_logic

DIST_DIR = dist/latest VHDL_DIR = VHDL VERILOG_DIR = Verilog FREERAM_DIR = ../ramlib/VHDL WWW_SOURCE = /WINDOWS/Profiles/dk/My\ Documents/My\ Webs/myweb4/risc8 WWW_DEST = www COPY = cp COPYDI

../../../bench/verilog/tb_ethernet.v ../../../bench/verilog/tb_eth_defines.v ../../../bench/verilog/eth_phy.v ../../../bench/verilog/eth_phy_defines.v ../../../bench/verilog/wb_bus_mon.v ../../..

+libext+.v +access+wr +mess +incdir+../../../rtl/verilog+../../../bench/verilog +tcl+../bin/sim.tcl -y ../../../rtl/verilog -y ../../../bench/verilog ../../../bench/verilog/uart_test.v //+gui