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library verilog; use verilog.vl_types.all; entity clk_gen is generic( S1 : integer := 1; S2 : integer := 2; S3 : integer := 4;

library verilog; use verilog.vl_types.all; entity adder4 is port( cout : out vl_logic; sum : out vl_logic_vector(3 downto 0); ina :

library verilog; use verilog.vl_types.all; entity pll1 is port( inclock : in vl_logic; locked : out vl_logic; clock0 : out vl_logic;

library verilog; use verilog.vl_types.all; entity ddr_sdram is port( clk : in vl_logic; reset_n : in vl_logic; addr : in vl_logic

library verilog; use verilog.vl_types.all; entity chuli is port( shu_in : in vl_logic_vector(8 downto 0); shu_out : out vl_logic_vector(7 downto 0) ); e

library verilog; use verilog.vl_types.all; entity lian is port( Aim_in : in vl_logic_vector(7 downto 0); Are_in : in vl_logic_vector(7 downto 0);

library verilog; use verilog.vl_types.all; entity clkgen is port( phi1 : out vl_logic; phi2 : out vl_logic ); end clkgen;

library verilog; use verilog.vl_types.all; entity stackc is port( clk : in vl_logic; nrst : in vl_logic; push : in vl_logic;

library verilog; use verilog.vl_types.all; entity mem96x96x16 is generic( row : integer := 96; col : integer := 96; rowsize : integer := 7;

library verilog; use verilog.vl_types.all; entity ibufg_sstl3_i is generic( cds_action : string := "ignore" ); port( o : out vl_logic; i