_primary.vhd

在ise下设计的蝶形变换程序

library verilog;
use verilog.vl_types.all;
entity lian is
    port(
        Aim_in          : in     vl_logic_vector(7 downto 0);
        Are_in          : in     vl_logic_vector(7 downto 0);
        Bim_in          : in     vl_logic_vector(7 downto 0);
        Bre_in          : in     vl_logic_vector(7 downto 0);
        clk             : in     vl_logic;
        cms_in          : in     vl_logic_vector(8 downto 0);
        cps_in          : in     vl_logic_vector(8 downto 0);
        c_in            : in     vl_logic_vector(7 downto 0);
        Dim_out         : out    vl_logic_vector(7 downto 0);
        Dre_out         : out    vl_logic_vector(7 downto 0);
        Eim_out         : out    vl_logic_vector(7 downto 0);
        Ere_out         : out    vl_logic_vector(7 downto 0)
    );
end lian;