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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity apex20ke_dpram is
generic(
operation_mode : string := "single_port";
output_mode : string := "reg";
width
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity b5mux21 is
port(
\MO\ : out vl_logic_vector(4 downto 0);
\A\ : in vl_logic_vector(4 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity altaccumulate is
generic(
width_in : integer := 4;
width_out : integer := 8;
lpm_representation: string := "
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ram7x20_syn is
generic(
ram_width : integer := 20
);
port(
wclk : in vl_logic;
rst_l
_info
m255
cModel Technology
dD:\quartus_30\quartus\tpi\mgc_oem
vdeskew_ram_block
ISPnKC;K_QX
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_dec_4b is
port(
datain : in vl_logic_vector(4 downto 0);
k28 : in vl_logic;
potctl
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity flex10ke_lcell is
generic(
operation_mode : string := "normal";
output_mode : string := "reg_and_comb";
packed_mode
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity b5mux21 is
port(
\MO\ : out vl_logic_vector(4 downto 0);
\A\ : in vl_logic_vector(4 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity apexii_io is
generic(
operation_mode : string := "input";
ddio_mode : string := "none";
open_drain_output: string
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity apexii_pll is
generic(
operation_mode : string := "normal";
simulation_type : string := "timing";
clk0_multiply_by: int