📄 _info

📁 一个非常好的dc使用书籍一个非常好的dc使用书籍
💻
字号:
m255cModel TechnologydD:\quartus_30\quartus\tpi\mgc_oemvdeskew_ram_blockISPnKC;K_QX<f3fkzXA`322V`CWofhX;RUid82hk6J;gb3d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 8551OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vdivide_by_twoIjkDgBnPQQmOOcZ7<V=YfO1Vham^]OM@zH@0Qn`VzWZ_?3d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 2678OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vmux4IX65RlR`]oj>2`h@i5L:TS3VA@S1PdVPTgBB5cVN>^UMj2d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 2663OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_8b10b_decoderIRRaKdO9HR3=z@bb>Y[9d^3VA;@X6<^iB2n]cGOnjbOFS0d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 7206OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_8b10b_encoderI3I?7O^nN=1Q2:Ck6e@D^Q1VTmFgHmkVkJ@co7M^Ve8Fb1d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 6931OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_comp_fifoIoi:OAZSOo_^;h^QdfoZoH2V<Vcb]^8]HfHRY28ZY:NCh2d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 7366OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_comp_fifo_coreINaj:n>0LO@Q[INQGBQGE]1VhZhL12c92zzngKe1Xg`<@2d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 7519OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_comp_fifo_smI<k[^_Un]mZ1RTO4>ioAOi2V?61[cnoYM7BZma5himIV12d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 8154OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_dec_4bIQ`g61JD7[^>R`o]j8]KJ11VGi3JR[j`K>fF^Wo_fJAOC3d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 7108OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_dec_6bIDg>Lca9FQIE]jcdT[3`:C0V_78ajGn>l3_]3ZKA_mS1Y3d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 7149OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_deskew_fifoI>aL9=0SQ163hWed?DFfBA1VQCihXTF31KZ2983ZC8am>0d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 8267OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_enc_3bIJCYNiRi]TA8BlW:83@fV;2V?I^0]OEBo2=a=1KG<>QJN0d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 6788OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_enc_5bIOiQX47HLl[O=O@RS;PFi91V28iXC88Sd`31a_6hnDB_M0d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 6854OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_hssi_receiverI54h4TnSXQkc?;SknW@gXi1ViSKJ8V?E`lkKCbMleQ<zo2d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 2717OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_hssi_rx_a1a1a2a2_patdet_smI?iAZ2VPGgg<B]2EE7NHI;2V[h=TGzg]m<g=kd@hgl_d^3d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 1248OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_hssi_rx_a1a2_align_smI36i4cVA2h7ZaaOLXkSP1l2Vl2CO^^_MZjEJ2dbD^aZTm3d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 1149OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_hssi_rx_a1a2_patdetIJI]?OPXDSFQQF1aVO>k]G0VQ=WVjUePFLzE?CQO086oD3d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 1316OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_hssi_rx_serdesIZ[QUJXVbBao284n[0]f6e1VNT[nH8R[=4GaEhNI5AHI_1d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 2318OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_hssi_rx_sync_smInPAiL==S5;=[4N7FE8M:f0Vb6TYZSDa^26Z]fI3QNoi`2d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 675OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_hssi_symbol_alignerIAR3jZ=<^Fi;OjcJj5iKGd1VThFUJ_F[DSWo^oF76O0n?0d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 1487OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_hssi_transmitterIVJDS:Z5M[TezZJn5dXgd13Vfn9>a:CNCb6O<2ihfXOWj0d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 3715OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_hssi_tx_serdesIPgnloVkBPS8N:_5EJCMUO2Vz>ZCZW8c>l=O`hQ8Q[jhU1d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 3583OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_hssi_word_alignerINMM36SeHnA[_;@l9N]oZL2VF=AC;>8TK`m6<kakAXI<T2d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 2187OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_l04IdoBPKNnGM;GEDlk?dYZPY1VUdKKYEGFUT3;n];L:3Kmi1d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 8805OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_l13INQMRV<6ogndFW^Woz8mMO1VNm1<CGc[F_Uj0D8<6VG5X0d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 8817OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_l22IF^h_j^HFYk3S1gj2iWPm>3V0=f_K>Wzc5bm4YV]R@gS^2d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 8832OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_l31IGLm_XT0e<ae<YaVWafVbF0VX9:A`V8B8bH5VTVX_kJdn2d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 8848OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_l40IKP>ZJ7lfkOb<f`Mi@3O9c3V5lHU2FGERKZRlA^i3Vd?62d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 8862OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_parity_4bIFIl?eKLR;o^_HFQE]j]hV0V4f03K3CiXOV_ACH=Hzo7C0d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 8919OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_parity_6bImecz^O1EF?gAo4l`210GJ2VooKN<:WEkQ?iPSZTJZCKb2d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 8990OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_parity_checkIzVY`W]MJK<Dk2J4S7BkL]0VJ<C=<PPC:_^eaPzm2[biZ0d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 9073OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_reset_blockI524GzI<?^kWVdnFg0S8;Y3V[1>HX16B=D^5<MB^>QKi[1d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 6352OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_rx_coreI2083SIOSS?FGMh_5QbeY72VGCMc=fG8jI8a3Z^En271n2d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 301OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_t02I`igeDQb6c:Wg12PVQCz8V2VY2@P7gj>9]PX5mEGcW6if1d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 8874OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_t11I<52lWMCm>iMc4H:7i_o2@0V25XWN1cEUdFCW[gzo=]0[2d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 8886OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_t20I`J3FE^fSN`@aQRJGoXYhi3VFRnc<?PXLJn<PjTGaMOG61d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 8898OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_tx_coreIV3C5UhC:@5Z2K:SUk=cif3VF7n[0i;_T2KWnF^R8=9h70d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 32OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_xgm_dskw_smILf3XAHbOjg9SN56YTbl:?1VnNB9:H92RQ0E[<jTG1`J93d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 6086OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_xgm_interfaceIW`aG2h_TAnVkFOFLXoJ0F1VAW6=5NjM:__Lfi@2>MGYC1d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 6419OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_xgm_rx_smICPES3NVA>G9oK=5meF92Y3VVd8;Xe<VFFMK^CXR0B=8R2d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 4078OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0vstratixgx_xgm_tx_smI0Q@]dhfJP>jkIEjXe2HSA1VaT19hK5B_[[N:0L`VHlUE3d.FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v)L0 4651OV;L;5.7c;17r131o-93 -work D:/quartus_30/quartus/tpi/mgc_oem/libs/altera/Verilog/stratixgx_gxb -path QuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_hssi_atoms.v) -O0
⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -