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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity armtst is
generic(
wordwidth_data : integer := 16;
memsize_data : integer := 32
);
port(
clkin : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity top is
generic(
wordwidth_data : integer := 16;
memsize_data : integer := 32
);
port(
clkin : in
lfsr6s3.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: lfsr6s3.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//**********************************************
lfsr6s3.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: lfsr6s3.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//**********************************************
lfsr6s3.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: lfsr6s3.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//**********************************************
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity a_task is
port(
clk_2_5m : in vl_logic;
rst : in vl_logic;
nd_a : in vl_logic;
ps2rs232.qsf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
clkscan3.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
clkscan1.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
clkscan2.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any