_primary.vhd

Verilog编程

library verilog;
use verilog.vl_types.all;
entity top is
    generic(
        wordwidth_data  : integer := 16;
        memsize_data    : integer := 32
    );
    port(
        clkin           : in     vl_logic;
        rst             : in     vl_logic;
        ncs0_n          : in     vl_logic;
        nwe_n           : in     vl_logic;
        addr            : in     vl_logic_vector(4 downto 0);
        datain          : in     vl_logic_vector(15 downto 0);
        sine1           : out    vl_logic_vector(7 downto 0);
        sine2           : out    vl_logic_vector(7 downto 0);
        sine3           : out    vl_logic_vector(7 downto 0);
        sine4           : out    vl_logic_vector(7 downto 0);
        sine5           : out    vl_logic_vector(7 downto 0);
        sine6           : out    vl_logic_vector(7 downto 0);
        clk_out         : out    vl_logic
    );
end top;