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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity b5mux21 is
port(
mo : out vl_logic_vector(4 downto 0);
a : in vl_logic_vector(4 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lpm_counter is
generic(
lpm_width : integer := 1;
lpm_direction : string := "UNUSED";
lpm_modulus : integer :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity disp_ram is
port(
addra : in vl_logic_vector(14 downto 0);
addrb : in vl_logic_vector(14 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity myclock is
port(
CLKIN_IN : in vl_logic;
RST_IN : in vl_logic;
CLK0_OUT : out vl_logic;
nand_interface.hif
Version 7.2 Build 151 09/26/2007 SJ Full Version
39
2318
OFF
OFF
OFF
OFF
ON
ON
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Pat
vgatest.tbw
version 3
D:/Xilinx/basys/VGAVGA/vga.v
vga
VERILOG
VERILOG
vgatest.xwv
Clocked
-
-
1000000000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
clk
20000000
20000000
3000000
300
lfsr6s3.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: lfsr6s3.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//**********************************************
lfsr6s3.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: lfsr6s3.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//**********************************************
lfsr6s3.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: lfsr6s3.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//**********************************************
fft_test.vif
#
# Synplicity Verification Interface File
# Generated using Synplify-pro
#
# Copyright (c) 1996-2005 Synplicity, Inc.
# All rights reserved
#
# Set logfile options
vif_set_result_file fft_