fft_test.vif

用vhdl编写的FFT的代码,很全,很强大.

#
# Synplicity Verification Interface File
# Generated using Synplify-pro
#
# Copyright (c) 1996-2005 Synplicity, Inc.
# All rights reserved
#

# Set logfile options
vif_set_result_file  fft_test.vlf

# Set technology for TCL script
vif_set_technology -architecture FPGA -vendor Xilinx

# RTL and technology files
 
vif_add_library -original $XILINX/verilog/verification/unisims
vif_add_library -original $XILINX/verilog/verification/simprims
vif_add_file -original -verilog C:\Program Files\Synplicity\fpga_85\bin\..\lib\xilinx\unisim.v
vif_add_file -original -verilog ./fft_test.v
vif_set_top_module -original -top fft_test
 
vif_add_library -translated $XILINX/verilog/verification/unisims
vif_add_library -translated $XILINX/verilog/verification/simprims
vif_add_file -translated -verilog fft_test.vm
vif_set_top_module -translated -top fft_test 
# Read FSM encoding

# Memory map points

# SRL map points

# Compiler constant registers

# Compiler constant latches

# Compiler RTL sequential redundancies

# RTL sequential redundancies

# Technology sequential redundancies

# Inversion map points

# Port mappping and directions

# Black box mapping
vif_set_black_box fft
vif_set_black_box ram

vif_set_map_point -blackbox -original u1 -translated u1
vif_set_map_point -blackbox -original u2 -translated u2

# Other sequential cells, including multidimensional arrays

# Constant Registers

# Retimed Registers