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Verilog 的代码
uart_emitter.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
usrt_receive.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity clk_div is
generic(
n : integer := 9
);
port(
clk : in vl_logic;
rstn : i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity clk_gen is
port(
clk : in vl_logic;
rstn : in vl_logic;
clk_o : out vl_logic
hb_cmds
-proj d:\verilog\ise_test
-t test_ddr_command.tbw
-source ddr_command.v
-entity ddr_command
-ipcport 1111
ise_test.npl
JDF G
// Created by Project Navigator ver 1.0
PROJECT ise_test
DESIGN ise_test
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s200
DEVICETIME 1187056968
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -5
DEVSPE
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_crcblock is
generic(
oscillator_divider: integer := 1
);
port(
clk : in vl_logic;
shiftnld
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_mac_mult is
generic(
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string :
boshuwave_bencher.prj
verilog work "../xilinx/complexmul.v"
verilog work "boshuxc.v"
verilog work D:/Xilinx/verilog/src/glbl.v
run.sh
#!/bin/sh
ncverilog -q \
+incdir+../../../bench/verilog/ -v ../../../bench/verilog/*.v \
+incdir+../../../rtl/verilog/ -v ../../../rtl/verilog/*.v