uart_emitter.map.qmsg

Uart port 是一段不错的

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 11 21:40:37 2006 " "Info: Processing started: Mon Dec 11 21:40:37 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off uart_emitter -c uart_emitter " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off uart_emitter -c uart_emitter" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "E:/verilog/uart_ser_to_bing/uart_emitter.v " "Warning: Can't analyze file -- file E:/verilog/uart_ser_to_bing/uart_emitter.v is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_emitter.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file uart_emitter.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_emitter " "Info: Found entity 1: uart_emitter" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "uart_emitter " "Info: Elaborating entity \"uart_emitter\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|uart_emitter\|state 12 " "Info: State machine \"\|uart_emitter\|state\" contains 12 states" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|uart_emitter\|state " "Info: Selected Auto state machine encoding method for state machine \"\|uart_emitter\|state\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|uart_emitter\|state " "Info: Encoding result for state machine \"\|uart_emitter\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "12 " "Info: Completed encoding using 12 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.over " "Info: Encoded state bit \"state.over\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.bit0 " "Info: Encoded state bit \"state.bit0\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.bit1 " "Info: Encoded state bit \"state.bit1\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.bit2 " "Info: Encoded state bit \"state.bit2\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.bit3 " "Info: Encoded state bit \"state.bit3\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.bit4 " "Info: Encoded state bit \"state.bit4\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.bit5 " "Info: Encoded state bit \"state.bit5\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.bit6 " "Info: Encoded state bit \"state.bit6\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.bit7 " "Info: Encoded state bit \"state.bit7\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.bit8 " "Info: Encoded state bit \"state.bit8\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.bit9 " "Info: Encoded state bit \"state.bit9\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.idle " "Info: Encoded state bit \"state.idle\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_emitter\|state.idle 000000000000 " "Info: State \"\|uart_emitter\|state.idle\" uses code string \"000000000000\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_emitter\|state.bit9 000000000011 " "Info: State \"\|uart_emitter\|state.bit9\" uses code string \"000000000011\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_emitter\|state.bit8 000000000101 " "Info: State \"\|uart_emitter\|state.bit8\" uses code string \"000000000101\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_emitter\|state.bit7 000000001001 " "Info: State \"\|uart_emitter\|state.bit7\" uses code string \"000000001001\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_emitter\|state.bit6 000000010001 " "Info: State \"\|uart_emitter\|state.bit6\" uses code string \"000000010001\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_emitter\|state.bit5 000000100001 " "Info: State \"\|uart_emitter\|state.bit5\" uses code string \"000000100001\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_emitter\|state.bit4 000001000001 " "Info: State \"\|uart_emitter\|state.bit4\" uses code string \"000001000001\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_emitter\|state.bit3 000010000001 " "Info: State \"\|uart_emitter\|state.bit3\" uses code string \"000010000001\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_emitter\|state.bit2 000100000001 " "Info: State \"\|uart_emitter\|state.bit2\" uses code string \"000100000001\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_emitter\|state.bit1 001000000001 " "Info: State \"\|uart_emitter\|state.bit1\" uses code string \"001000000001\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_emitter\|state.bit0 010000000001 " "Info: State \"\|uart_emitter\|state.bit0\" uses code string \"010000000001\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|uart_emitter\|state.over 100000000001 " "Info: State \"\|uart_emitter\|state.over\" uses code string \"100000000001\"" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 9 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "uart_emitter.v" "" { Text "E:/verilog/uart/uart_emitter.v" 5 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "41 " "Info: Implemented 41 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "11 " "Info: Implemented 11 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "2 " "Info: Implemented 2 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "28 " "Info: Implemented 28 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 11 21:40:42 2006 " "Info: Processing ended: Mon Dec 11 21:40:42 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}