usrt_receive.map.qmsg

Uart port 是一段不错的

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 11 21:45:58 2006 " "Info: Processing started: Mon Dec 11 21:45:58 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off usrt_receive -c usrt_receive " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off usrt_receive -c usrt_receive" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "usrt_receive.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file usrt_receive.v" { { "Info" "ISGN_ENTITY_NAME" "1 usrt_receive " "Info: Found entity 1: usrt_receive" {  } { { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "usrt_receive " "Info: Elaborating entity \"usrt_receive\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|usrt_receive\|state 3 " "Info: State machine \"\|usrt_receive\|state\" contains 3 states" {  } { { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 25 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|usrt_receive\|state " "Info: Selected Auto state machine encoding method for state machine \"\|usrt_receive\|state\"" {  } { { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 25 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|usrt_receive\|state " "Info: Encoding result for state machine \"\|usrt_receive\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "3 " "Info: Completed encoding using 3 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.idle " "Info: Encoded state bit \"state.idle\"" {  } { { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 25 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.receving " "Info: Encoded state bit \"state.receving\"" {  } { { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 25 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.starting " "Info: Encoded state bit \"state.starting\"" {  } { { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 25 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|usrt_receive\|state.idle 000 " "Info: State \"\|usrt_receive\|state.idle\" uses code string \"000\"" {  } { { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 25 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|usrt_receive\|state.receving 110 " "Info: State \"\|usrt_receive\|state.receving\" uses code string \"110\"" {  } { { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 25 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|usrt_receive\|state.starting 101 " "Info: State \"\|usrt_receive\|state.starting\" uses code string \"101\"" {  } { { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 25 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "usrt_receive.v" "" { Text "E:/verilog/uart/usrt_receive.v" 25 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "81 " "Info: Implemented 81 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "33 " "Info: Implemented 33 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "44 " "Info: Implemented 44 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 11 21:46:04 2006 " "Info: Processing ended: Mon Dec 11 21:46:04 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}