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#-- Synplicity, Inc. #-- Version Synplify Pro 8.1 #-- Project file D:\altera\lvds\proj.prj #-- Written on Tue Nov 07 00:52:40 2006 #add_file options add_file -verilog "D:/altera/lvds/tx.v" a

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Runni

library verilog; use verilog.vl_types.all; entity se_pa_tst is generic( PERIOD : integer := 200; DUTY_CYCLE : real := 0.500000; OFFSET : integer :

library verilog; use verilog.vl_types.all; entity pa_se_tst is generic( PERIOD : integer := 200; DUTY_CYCLE : real := 0.500000; OFFSET : integer :

# # Synplicity Verification Interface File # Generated using Synplify-pro # # Copyright (c) 1996-2005 Synplicity, Inc. # All rights reserved # # Set logfile options vif_set_result_file Mult

JDF G // Converted from an earlier version by Project Navigator version 5 PROJECT fifoctrl_v DESIGN fifo_v Normal DEVFAM virtex DEVFAMTIME 1016217226 DEVICE xcv50 DEVICETIME 1016217226 DEVPKG

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}