state_machine.map.qmsg

用verlog语言编的一些基础实验,适合于FPGA/CPLD的初学者。内容包括8位优先编码器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 14 11:11:30 2005 " "Info: Processing started: Wed Dec 14 11:11:30 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off state_machine -c state_machine " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off state_machine -c state_machine" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "state_machine.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file state_machine.v" { { "Info" "ISGN_ENTITY_NAME" "1 state_machine " "Info: Found entity 1: state_machine" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/简单状态机/state_machine.v" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "state_machine " "Info: Elaborating entity \"state_machine\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 state_machine.v(25) " "Warning: Verilog HDL assignment warning at state_machine.v(25): truncated value with size 32 to match size of target (8)" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/简单状态机/state_machine.v" 25 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 state_machine.v(31) " "Warning: Verilog HDL assignment warning at state_machine.v(31): truncated value with size 32 to match size of target (24)" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/简单状态机/state_machine.v" 31 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 state_machine.v(34) " "Warning: Verilog HDL assignment warning at state_machine.v(34): truncated value with size 32 to match size of target (24)" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/简单状态机/state_machine.v" 34 0 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt\[0\]~0 24 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=24) from the following logic: \"cnt\[0\]~0\"" {  } { { "state_machine.v" "cnt\[0\]~0" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/简单状态机/state_machine.v" 23 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|state_machine\|state 8 0 " "Info: State machine \"\|state_machine\|state\" contains 8 states and 0 state bits" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|state_machine\|state " "Info: Selected Auto state machine encoding method for state machine \"\|state_machine\|state\"" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|state_machine\|state " "Info: Encoding result for state machine \"\|state_machine\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "3 " "Info: Completed encoding using 3 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state~48 " "Info: Encoded state bit \"state~48\"" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state~47 " "Info: Encoded state bit \"state~47\"" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state~46 " "Info: Encoded state bit \"state~46\"" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0}  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|state_machine\|state.state0 000 " "Info: State \"\|state_machine\|state.state0\" uses code string \"000\"" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|state_machine\|state.state6 110 " "Info: State \"\|state_machine\|state.state6\" uses code string \"110\"" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|state_machine\|state.state5 101 " "Info: State \"\|state_machine\|state.state5\" uses code string \"101\"" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|state_machine\|state.state4 100 " "Info: State \"\|state_machine\|state.state4\" uses code string \"100\"" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|state_machine\|state.state3 011 " "Info: State \"\|state_machine\|state.state3\" uses code string \"011\"" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|state_machine\|state.state2 010 " "Info: State \"\|state_machine\|state.state2\" uses code string \"010\"" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|state_machine\|state.state1 001 " "Info: State \"\|state_machine\|state.state1\" uses code string \"001\"" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|state_machine\|state.state7 111 " "Info: State \"\|state_machine\|state.state7\" uses code string \"111\"" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0}  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "c\[0\] VCC " "Warning: Pin \"c\[0\]\" stuck at VCC" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/简单状态机/state_machine.v" 8 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[0\] GND " "Warning: Pin \"en\[0\]\" stuck at GND" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/简单状态机/state_machine.v" 10 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[1\] GND " "Warning: Pin \"en\[1\]\" stuck at GND" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/简单状态机/state_machine.v" 10 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[2\] GND " "Warning: Pin \"en\[2\]\" stuck at GND" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/简单状态机/state_machine.v" 10 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[3\] GND " "Warning: Pin \"en\[3\]\" stuck at GND" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/简单状态机/state_machine.v" 10 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[4\] GND " "Warning: Pin \"en\[4\]\" stuck at GND" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/简单状态机/state_machine.v" 10 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[5\] GND " "Warning: Pin \"en\[5\]\" stuck at GND" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/简单状态机/state_machine.v" 10 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[6\] GND " "Warning: Pin \"en\[6\]\" stuck at GND" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/简单状态机/state_machine.v" 10 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[7\] GND " "Warning: Pin \"en\[7\]\" stuck at GND" {  } { { "state_machine.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/基础实验/简单状态机/state_machine.v" 10 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "rst " "Info: Promoted clear signal driven by pin \"rst\" to global clear signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "61 " "Info: Implemented 61 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "43 " "Info: Implemented 43 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 14 11:11:33 2005 " "Info: Processing ended: Wed Dec 14 11:11:33 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}