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jishu0.qsf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
internal_buffer.v
//
// Verilog Module dwt_final_lib.internal_buffer.arch_name
//
// Created:
// by - VLSI4.UNKNOWN (VLSI04)
// at - 15:10:00 03/29/2008
//
// using Mentor Graphics HDL Designer
vopt8kcesn
library verilog;
use verilog.vl_types.all;
entity bldcm_con_tb is
generic(
CLK_PERIOD : integer := 2;
S0 : integer := 0;
S1 : integer := 4;
vopt4gsb5q
library verilog;
use verilog.vl_types.all;
entity bldcm_con_tb is
generic(
CLK_PERIOD : integer := 2;
S0 : integer := 0;
S1 : integer := 4;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity bldcm_con_tb is
generic(
CLK_PERIOD : integer := 2;
S0 : integer := 0;
S1 : integer := 4;
config_dac.qsf
# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
counter_16_bits.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
main.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
pulse_16_sum.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
data_mux.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus