internal_buffer.v

it is used to find traffic

//
// Verilog Module dwt_final_lib.internal_buffer.arch_name
//
// Created:
//          by - VLSI4.UNKNOWN (VLSI04)
//          at - 15:10:00 03/29/2008
//
// using Mentor Graphics HDL Designer(TM) 2004.1b (Build 12)
//
`resetall
`timescale 1ns/10ps
module internal_buffer ;


// ### Please start your Verilog code here ###
endmodule